The Universal Chiplet Interconnect Express (UCIe) Consortium has announced the release of the UCIe 2.0 specification, further advancing the open chiplet ecosystem.

The latest specification introduces several key enhancements. First, it adds support for a standardized system architecture for manageability, testability, and debugging (DFx) across multiple chipsets throughout the system-in-package (SiP) lifecycle. This includes an optional UCIe DFx Architecture (UDA) that integrates a vendor-agnostic management fabric within each chiplet for testing, telemetry and debug functions.

Additionally, UCIe 2.0 brings support for 3D packaging with hybrid bonding. The new UCIe-3D standard supports bump pitches ranging from as small as 1 micron up to 25 microns, enabling higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures.

"The UCIe Consortium is supporting a diverse range of chipsets to meet the needs of the rapidly changing semiconductor industry," said Cheolmin Park, President and Corporate vice president at Samsung Electronics.

The UCIe 2.0 Specification builds on previous iterations by developing a comprehensive solution stack and encouraging interoperability between chipset solutions.

The specification also includes optimized package designs to facilitate interoperability and compliance testing, allowing vendors to validate the supported features of their UCIe-based devices against a known reference implementation.

Notably, the UCIe 2.0 specification remains fully backwards compatible with UCIe 1.1 and 1.0, ensuring a smooth transition for existing chiplet-based designs.