Why std::atomic's store employs XCHG for sequential consistency

In the context of std::atomic for x86 and x86_64 architectures, a store operation with sequential consistency (std::memory_order_seq_cst) employs XCHG instead of a simple store with a memory barrier as the technique to achieve sequential-release semantics.

Sequential Consistency and xchg

Sequential consistency dictates that all memory operations appear to execute in some sequential order, and this order is the same for all threads. XCHG, an x86 instruction that atomically exchanges the values of two operands, inherently satisfies this sequential consistency requirement. By using XCHG to perform a write operation, std::atomic ensures that the store becomes globally visible to all threads at a specific point in the order of execution, preventing reordering with subsequent operations.

mov-store mfence vs. XCHG

While a simple mov-store followed by a memory fence (such as mfence) could theoretically provide release semantics, it is not sufficient for sequential-release store operations. MFENCE, a memory fence instruction that establishes a memory barrier, ensures that previous write operations are committed to memory before proceeding. However, it does not prevent subsequent load operations from being reordered before the release store.

Performance Considerations

The choice between mov-store mfence and XCHG for sequential-release store operations involves performance trade-offs.

• On certain CPUs (e.g., Intel Skylake), XCHG can be more efficient than mov-store mfence, especially when there is no surrounding dependent code that needs to synchronize with the atomic operation.
• On other CPUs, mov-store mfence may be preferable for high-throughput scenarios or when surrounding code can overlap execution with the atomic operation.

Implementation Details

In practice, the specific implementation of std::atomic's store with sequential consistency varies depending on the compiler and hardware architecture.

• GCC/Clang: Originally used mov-store mfence but have recently switched to using XCHG for seq-cst stores.
• Intel Compiler: Uses XCHG for seq-cst stores.
• Microsoft Visual C : Also uses XCHG for seq-cst stores.

Implicit Acquire Fence

The statement that x86 stores have an implicit acquire fence is incorrect. Stores on x86 have release semantics, not acquire semantics. Acquire semantics are typically enforced using memory barriers such as mfence or atomic read operations with std::memory_order_acquire semantics.